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Espressif Systems /ESP32-P4 /LP_AON_CLKRST /LP_AONCLKRST_HPCPU_RESET_CTRL0

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Interpret as LP_AONCLKRST_HPCPU_RESET_CTRL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN)LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN 0LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH 0 (LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN)LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN 0LP_AONCLKRST_HPCORE0_STALL_WAIT 0 (LP_AONCLKRST_HPCORE0_STALL_EN)LP_AONCLKRST_HPCORE0_STALL_EN 0 (LP_AONCLKRST_HPCORE0_SW_RESET)LP_AONCLKRST_HPCORE0_SW_RESET 0 (LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET)LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET 0 (LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL)LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL 0 (LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN)LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN 0LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH 0 (LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN)LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN 0LP_AONCLKRST_HPCORE1_STALL_WAIT 0 (LP_AONCLKRST_HPCORE1_STALL_EN)LP_AONCLKRST_HPCORE1_STALL_EN 0 (LP_AONCLKRST_HPCORE1_SW_RESET)LP_AONCLKRST_HPCORE1_SW_RESET 0 (LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET)LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET 0 (LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL)LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL

Description

need_des

Fields

LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN

write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature
LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH

need_des
LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN

write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature
LP_AONCLKRST_HPCORE0_STALL_WAIT

need_des
LP_AONCLKRST_HPCORE0_STALL_EN

need_des
LP_AONCLKRST_HPCORE0_SW_RESET

need_des
LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET

need_des
LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL

1’b1: boot from HP TCM ROM: 0x4FC00000 1’b0: boot from LP TCM RAM: 0x50108000
LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN

write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature
LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH

need_des
LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN

write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature
LP_AONCLKRST_HPCORE1_STALL_WAIT

need_des
LP_AONCLKRST_HPCORE1_STALL_EN

need_des
LP_AONCLKRST_HPCORE1_SW_RESET

need_des
LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET

need_des
LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL

1’b1: boot from HP TCM ROM: 0x4FC00000 1’b0: boot from LP TCM RAM: 0x50108000

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data